Speaker
Description
The project is conducted as a collaborative effort involving The rapid expansion of edge computing and AI-enabled IoT devices demands VLSI architectures that are not only energy-efficient but also resilient to process variations, aging effects, and momentary faults. The proposed novel Adaptive Self-Healing Neuromorphic-Inspired Very Large-Scale Integration (ASHN-VLSI) architecture integrates on-site health monitoring, machine-learning-driven fault prediction, and dynamic reconfigurable logic to enhance reliability while minimizing power consumption.
The proposed architecture introduces three key innovations: (1) distributed on-chip nanoscale health sensors embedded within standard cell libraries to monitor parameters such as threshold voltage drift, electromigration stress, and temperature hotspots; (2) a lightweight hardware neural predictor that anticipates aging-induced failures using realtime telemetry; and (3) a fine-grained reconfigurable fabric capable of dynamically rerouting critical logic paths and reallocating computational loads without interrupting system operation. Unlike conventional redundancy-based fault-tolerance techniques incuring high area and power overheads, the ASHN-VLSI framework leverages predictive analytics and localized reconfiguration to significantly reduce standby power and extend chip lifetime.
Fabricated using advanced FinFET technology nodes, the architecture demonstrates improved resilience against soft errors and process variability while maintaining subthreshold operational capability for ultra-low-power edge AI. Improvements in mean time to failure (MTTF), reduced leakage power, and enhanced energy-delay product could be achieved compared to traditional fault-tolerant designs.
| Academic or Professional Status | Faculty |
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