Speaker
Description
Power semiconductor devices generate substantial heat during operation, making thermal interface materials (TIMs) critical for maintaining performance and reliability. Conventional greases and pads, however, often suffer from poor mechanical stability, limited reusability, and inconsistent application. Here we present a scalable approach to fabricate architected polymer (P-TIMs) using high-resolution stereolithography (SLA) printing of a high-temperature resin loaded with boron nitride (BN) and glass microfibers. 3D polymer scaffolds with controlled microarchitectures including vertically oriented pillar arrays and lattice networks were printed and subsequently infiltrated with engineered thermal compounds to enhance through-plane heat conduction while maintaining electrical insulation and coefficient of thermal expansion (CTE) compatibility with semiconductor packages.
The P-TIMs were characterized for thermal, electrical, and mechanical performance. Thermal conductivity was measured using laser flash analysis and the transient plane source (TPS) method; dielectric strength and permittivity were evaluated with an LCR meter; mechanical response was assessed via tensile and compression testing; and CTE was determined by dilatometry. Device-level performance was evaluated using a chip-based test setup to quantify junction-to-case temperature reduction relative to commercial TIMs. Results demonstrate that scaffold geometry and filler composition enable repeatable control of interface thickness, compressibility, and through-plane thermal pathways, improving robustness and mitigating pump-out under thermal cycling.
| Academic or Professional Status | Postdoctoral Researcher / Research Scientist |
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